WP 5 is mainly devoted to the realization of a demonstrator at the 2X technology node able to prove the concept with the required statistics employing a large size test device. Furthermore the scalability of the concept to the 1X node will also be proven. To reach the goal, a first task T5.1 will address the modelling of the single cell device, the cell organization in the array and the full array description. The tool developed here will allow defining through simulations a proper array architecture that will be implemented in the real demonstrator in task T5.2. During this task a proper process flow will be set-up and the electrical characterization of the large array will be carried out. In the same task issues of compatibility with industrial realization will be addressed. Finally a scalability analysis will be performed in task 5.3, making use of both electrical characterization of miniaturized devices at 1X node and of the physical and electrical models developed in WP4 and WP5, focusing on the understanding of the performance of extremely scaled devices. Particular attention will be devoted to the scaling of power consumption and of transition speed.