The project aims at exploiting the potential of engineered Chalcogenide Superlatices to achieve a breakthrough in power dissipation and switching speed of Phase Change memories, towards a realization of a 'universal memory'.
Charge storage has been the main physical mechanism supporting all solid state mass storage
memories until now, both DRAM and FLASH. However none of the two main memory types
appear to fully satisfy system requirements, DRAM because of its volatility and large power
dissipation, and FLASH because of its slow programming speed and large block organization.
PCM (Phase Change Memory) technology is a promising candidate to target the 'universal memory' matching most of the properties of FLASH and DRAM. However, to realize the full
potential of PCM two crucial memory characteristics have to be improved: programming
current and switching speed.
The new memory concept investigated in the project is based on engineered Chalcogenide
SuperLattices (CSL) that should allow realizing the memory switching with a modification in the
bonding nature instead of the energy expensive melting process, bringing about a significant
reduction of both transition times and programming currents. Despite the convincing
experimental evidence the physical mechanism is not yet understood.
The project aims at exploiting the potential of CSL-PCM memory cells, starting from an
atomistic understanding of switching in CSL materials through experiments and physical model
development, leading to new insights for CSL engineering. Optimization of the CSL device will
be achieved through the development of a test vehicle allowing the benchmark among
different stacks, based on 'universal memory' electrical performance targets. A large array,
realized at 2X technology node, will be fabricated and integration issues will be addressed.
Scalability to the 1X node will be also evaluated to demonstrate the capability to become a real
“universal memory” also for the next generations of memory chips.
At the end of the project a first 'universal memory' chip at the state of the art technology node
will be available with an expected direct impact on the solid state memory market.